댓글 달아주신 님 말씀대로(^^) 문장 나눠서 어찌저찌 영어로 번역했어요;;;
(영어는 정말 힘들어요ㅠㅠ)

문법이랑 단어 쓰임이 맞는지...;; 여전히 의문스럽네요ㅠㅠ

한번 봐주시고 고칠부분 지적 해주시면 ......(__)!




This paper describes a new phase-locked loop(PLL) architecture with current compensating charge pump(CP) structure to minimize phase noise for wireless communications.

The proposed PLL has two CPs, main-CP(MCP) and sub-CP(SCP).

The SCP current pulse with same width and opposite sign of MCP is injected to the loop filter(LF), the disturbance on the voltage-controlled oscillator(VCO) control line can be minimized. In result, the PLL achieves low phase noise.

Also it adaptively controls the loop bandwidth according to the locking status using pulse width controller(PWC) and charge pump controller(CPC) for driving CP.

The proposed PLL is designed based on the 0.35um CMOS process with a 3.3V supply voltage.

HSPICE simulation shows 30us locking time and disturbance of VCO control line reduced over 0.5mV.